The present invention relates to a peaking circuit and a peaking adjustment method for controlling the occurrence of the peaking in a driver circuit (driver circuit for printed circuit board signal transmission, LD (Laser Diode) driver circuit, etc.) having a high transmission rate (e.g., over 1 Gbps (gigabit per second)) or in a device (information-processing apparatus (server, router, etc.), measurement apparatus, optical module, etc.) employing such driver circuits. The present invention relates also to a differential amplifier, a laser diode driving circuit and a data-processing unit which are equipped with a peaking circuit.
Information-processing apparatus (servers, routers, etc.) and measurement apparatus of today are required to process more and more data per unit time. In such situation, research and development are being conducted actively to speed up the signal transmission between circuits on an LSI of a device, the signal transmission between LSIs or printed circuit boards of a device, and optical modules used for networks (LAN, WAN, etc.) connecting such devices.
However, the above speeding up is usually accompanied by distortion of signal waveforms (due to wiring capacitance of LSIs, capacitance at the pads of LSIs, laser diodes, LSI packages, etc. and signal loss occurring in printed circuit boards and signal transmission lines such as cables), which leads to data errors.
A technique for compensating for the signal waveform distortion has been disclosed in Japanese Patent Laid-Open Publication No. 2005-136453, for example.
In Japanese Patent Laid-Open Publication No. HEI9-64920, a waveform shaping circuit for shaping the signal waveform of a pulse signal sequence is equipped with a gain-frequency characteristic circuit section which has its peaking property in a high-frequency part of the required frequency range. With the gain-frequency characteristic circuit section, the waveform shaping circuit performs the waveform shaping so that the amplitude of fast signal components becomes larger than that of slow signal components of the input.
A peaking control circuit disclosed in WO2007/110915 is equipped with a peaking detection unit for detecting the amount of the peaking (hereinafter referred to as “peaking level”) of an output section of an inductor peaking circuit and a control signal generating unit for varying the circuit parameters of the inductor peaking circuit based on the peaking level detected by the peaking detection unit.
A diode driver circuit described in Japanese Patent Laid-Open Publication No. HEI11-40855 is provided with a peaking current generating circuit.
However, the aforementioned technique of Japanese Patent Laid-Open Publication No. 2005-136453 is hardly usable for adjusting the peaking after the assembly into a package since the technique employs bonding wires.
Further, even though high-speed transmission circuits over 10 Gbps (gigabits per second) require compensation for the deterioration in the frequency characteristics caused by wiring impedance, parasitic capacitance occurs in transistor circuits like those described in Japanese Patent Laid-Open Publication No. HEI9-64920 and WO2007/110915. The parasitic capacitance, which is practically negligible in a relatively low-frequency range (below 1 Gbps), becomes nonnegligible in a high-frequency range over 10 Gbps. This makes the compensation for the frequency characteristics deterioration more and more difficult.
Moreover, peaking adjustment employing the circuitry described in Japanese Patent Laid-Open Publication No. HEI11-40855 results in a considerable increase in power consumption.